1. Field of the Invention
The present invention generally relates to computer systems and, more particularly, to a method and apparatus for reducing interrupt latencies associated with input/output operations.
2. Description of the Related Art
A conventional computer system 10 is shown in FIG. 1 and includes one or more central processing units (CPUs) 12a, 12b and 12c; a main memory unit 14 (such as random-access memory or RAM) that is used by the processing units to carry out program instructions; and one or more input/output (I/O) units 16a, 16b, and 16c, such as a display monitor, keyboard, pointing device (mouse), and a permanent memory device (such as a hard disk or floppy diskette) for storing the computer's operating system and user programs. Computer system 10 may have many additional components which are not shown, such as serial and parallel ports for connection to, e.g., modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter might be used with a video display monitor, or a memory controller might be used with memory 14. Also, processing units 12a, 12b and 12c may each be comprised of several components, such as the processor core (which includes various registers and logic units), one or more memory caches, and a bus interface.
In earlier computer systems, the processing unit(s) communicated with the other devices by a single system bus 18, but later computer systems eased loading of the system bus by providing a second, I/O bus 20, which is connected to the various I/O devices 16a, 16b, and 16c and to system bus 18 by a bus bridge 22. I/O bus 20 may be any suitable bus useful for interconnecting the various I/O devices mentioned above as well as other devices such as a local-area network (LAN) adapter. Exemplary bus standards include the ISA (industry standard architecture) bus, the EISA (extended industry standard architecture) bus, and the PCI (peripheral component interconnect) bus. Other means can also be provided for the various system devices to communicate with each other, such as direct memory access (DMA) channels which allow devices to communicate directly with one another, i.e., bypassing the processing units.
During I/O operations, various I/O devices (or the software device drivers controlling them) may issue "interrupt" signals to cause a processing unit to suspend its current procedure and save its status, and temporarily transfer control to a special routine such as an interrupt handler which then carries out a particular set of predetermined instructions to attend to the cause of the interrupt. Interrupts can occur during normal device operation, or due to abnormal (unexpected) circumstances, i.e., an "exception." A processor can further receive multiple interrupts from different sources; in which case, a set of interrupt priorities is used to determine which signal is handled first. After handling of the interrupt signal, control returns to the procedure that was being executed by the processing unit.
Many advances have allowed computer systems to operate at higher speeds, such as by increasing cache size and complexity. It is not always possible, however, to take full advantage of these speed gains due to other problems, such as the frequency of I/O operations. Two components of I/O operations that slow a system down are the interrupt processing delays (latencies) and the relatively slow operation of the I/O busses. For example, even on a PCI bus running at 33 MHz, an average "write" operation takes about 180 ns to complete; this is equal to 34 instructions on a 200 MHz processor. The ratio grows larger with tiered bus structures and distributed I/O devices. Also, new adapter cards are placing shorter interrupt latency requirements on systems, due to faster communication line speeds and faster devices. Again, this problem is multiplied in a tiered-bus structure.
To address the latency problems associated with I/O operations, some computer systems add special hardware for dealing with interrupt handling outside of the main processing unit(s). For example, the AS/400 computing system marketed by International Business Machines Corp. employs an I/O processor (IOP) to move the interrupt processing closer to the I/O devices. A similar design, described in U.S. Pat. No. 5,548,730, uses an intelligent bridge that contains a full microprocessor and its supporting functions (memory control, bus control). It requires both non-volatile and volatile memory attached to boot the processor and run the functional code, and is thus a relatively expensive approach.
Another design is disclosed in U.S. Pat. No. 5,555,430 in which interrupts in a symmetric multi-processing (SMP) system are routed to a central interrupt control unit which interfaces directly with the processing units and the I/O devices. This approach does not fully address interrupt latency issues since it only allows the system to route the interrupt to a processor running the lowest priority task. See also U.S. Pat. Nos. 5,495,615, 5,530,891 and 5,555,420. All of these patents deal with the intelligent routing of interrupts, but not the servicing issues.
Yet another design for handling interrupts in an improved manner is shown in U.S. Pat. No. 5,473,763. According to that method, which may be the closest prior art to the present invention, interrupt vectors are loaded directly into an address register to minimize overhead of processing interrupts. The address registers are located in "streamlined signal processors" which are part of the main processor complex. Provision of such a data-storage processor is relatively expensive, as with the above-noted approach. Also, providing a processor as part of the main CPU complex is more limiting, since it cannot be scaled for multi-bus systems, and still has the problems attributed to the I/O latency issues.
Generally, all of the foregoing solutions not only add to cost and complexity, but add to service response times because of the need to have the two processors converse. It would, therefore, be desirable to devise a method of reducing processor workload associated with servicing interrupts, so as to reduce interrupt service latency. It would be further advantageous if this effect were achieved at a lower cost than with full I/O processor designs.